SR Flip-Flop
A clocked SR flip-flop built from NAND gates. Pressing CLK ↑ triggers a rising-edge pulse — the flip-flop samples S and R and updates state. S = R = 1 is forbidden (both outputs go HIGH — indeterminate). Characteristic equation: Q(t+1) = S + R̄·Q(t), constraint SR = 0.
SR Flip-Flop — Clocked NAND
⚠ INVALID — S=R=1 Forbidden!
Q = 0
Q' = 1
Characteristic Table
| S | R | Q(t+1) | Operation |
|---|---|---|---|
| 0 | 0 | Q(t) | No Change ↗ |
| 0 | 1 | 0 | Reset ↓ |
| 1 | 0 | 1 | Set ↑ |
| 1 | 1 | ? | Invalid ✗ |
State History
| S | R | Q(t) | Q(t+1) | Result |
|---|---|---|---|---|
| — Press CLK ↑ to begin — | ||||
Q(t+1) = S + R̄·Q(t), SR = 0
Built from two cross-coupled NAND gates with AND input steering for the clock. The constraint S·R = 0 must always be satisfied.
Why is S=R=1 invalid?
Both NAND outputs are driven to 1 simultaneously. When CLK returns to 0, the final state depends on which gate is faster — race condition — making Q indeterminate.