D Flip-Flop
The D (Data) flip-flop is the simplest edge-triggered memory element. On every rising clock edge (CLK ↑), the output Q captures the value of D. Q' is always the complement. Q(t+1) = D — no forbidden states.
D Flip-Flop — Edge-Triggered
Characteristic Table
| D | CLK Edge | Q(t+1) | Operation |
|---|---|---|---|
| 0 | ↑ | 0 | Store 0 |
| 1 | ↑ | 1 | Store 1 |
| X | 0 or ↓ | Q(t) | No Change |
State History
| D | Q(t) | Q(t+1) | Result |
|---|---|---|---|
| — Press CLK ↑ to begin — | |||
Q(t+1) = D
The D flip-flop resolves the SR invalid state by connecting D to S and D̄ to R. This guarantees S and R are always complementary — no forbidden combination.
Uses in Practice
D flip-flops are the building blocks of registers, shift registers, pipeline stages, and every synchronous sequential circuit — CPUs, FPGAs, etc.
Setup & Hold Time
In real hardware, D must be stable before the clock edge (setup time) and remain stable after (hold time) for reliable capture.