Master-Slave JK Flip-Flop

A Master-Slave JK FF is two JK latches in series. The Master captures J/K on CLK = 1 (HIGH). The Slave transfers Master's output to Q on CLK = 0 (LOW). This two-phase capture eliminates the race-around condition of the simple JK FF.

Master-Slave JK — Two-Stage Design

CLK=1: CAPTURE MASTER 0 J CLK K Qm Qm' CLK=0: TRANSFER SLAVE 0 Qm CLK' Qm' Q Q' CLK̄ (inverted to Slave) 0 J 0 K CLK ↑↓ 0 Qm 1 0 Q 1 Q'
Qm = 0
Q = 0
Q' = 1

Characteristic Table

JKQ(t+1)Operation
00Q(t)No Change ↗
010Reset ↓
101Set ↑
11Q'(t)Toggle ⚡

Clock Cycle Simulation

① CLK 0→1: Master latches J, K → computes Qm
② CLK 1→0: Slave reads Qm → outputs Q, Q'
↑↓ button = complete 0→1→0 cycle

State History

JKQ(t)QmQ(t+1)Op
— Press CLK ↑↓ to begin —

Why Master-Slave?

In a simple JK FF with J=K=1, if CLK stays HIGH for a long time, the output can toggle multiple times in one cycle (race-around). The M-S design splits capturing (CLK=1) from outputting (CLK=0), ensuring exactly one transition per clock pulse.

Modern Alternative

Modern ICs use true edge-triggering (propagation delay-based) instead of Master-Slave, providing even more reliable single-edge operation used in all CMOS logic families today.