Multiplexer (MUX)
A 4:1 MUX routes one of four data inputs (I0–I3) to the output Y based on select lines S0, S1. Equivalent to a programmable switch. Implemented as IC 74HC153.
4:1 MUX — IC 74HC153
Routing: I0 → Y
S = 00
Y = 0
Selected input value: 0
Function Table
| S1 | S0 | Channel | Y Output |
|---|---|---|---|
| 0 | 0 | I0 | I0 |
| 0 | 1 | I1 | I1 |
| 1 | 0 | I2 | I2 |
| 1 | 1 | I3 | I3 |
When Enable (G̅) = 0, the selected input In is propagated to Y. When G̅ = 1, Y = 0 (disabled).
How MUX Works
Y = Isel where sel = S1·2 + S0
The select lines S0, S1 act like a 2-bit address, choosing which of the 4 data inputs to pass through.
Gate-level Implementation
Y = (S̄1·S̄0·I0) + (S̄1·S0·I1)
+ (S1·S̄0·I2) + (S1·S0·I3)
Applications
Data routing, parallel-to-serial conversion, function generators, bus arbitration, FPGA logic blocks.